1. Field of the Invention
The present invention relates to a synchronous delay circuit, and more specifically to a synchronous delay circuit having a reduced number of delay circuit stages in a delay circuit array by suppressing an increase of jitter.
2. Description of Related Art
As a background of the synchronous delay circuit to which the present invention is directed, a circuit for generating an internal clock in synchronism with an external clock by use of a delay circuit array used for measuring a time difference and another delay circuit array for reproducing a delay time corresponding to the measured time difference, will be described with reference to FIG. 1, which however illustrates one embodiment of the synchronous delay circuit in accordance with the present invention.
Referring to FIG. 1, the shown circuit includes a delay circuit array 101 used for measuring a time difference, another delay circuit array 102 for reproducing a delay time corresponding to the measured time difference, an input buffer 103 for receiving an external clock 106, a clock driver 104 for outputting an internal clock 107, and a dummy delay circuit 105 having a delay time corresponding to a sum of a delay time xe2x80x9ctd1xe2x80x9d of the input buffer 103 and a delay time xe2x80x9ctd2xe2x80x9d of the clock driver 104.
The delay circuit array 101 and the delay circuit array 102 are located in parallel to each other but to have a signal propagating direction opposite to each other in a synchronous delay circuit macro 108. The dummy delay circuit, 105 includes an input buffer dummy 105A constituted of completely the same circuit as the input buffer 103 (and therefore having the delay time xe2x80x9ctd1xe2x80x9d) and a clock driver dummy 105B constituted of completely the same circuit as the clock driver 104 (and therefore having the delay time xe2x80x9ctd2xe2x80x9d). The external clock (having the period of tCK) is caused to pass the input buffer 103 (delay time=td1) the dummy delay circuit (delay time=td1+td2), the synchronous delay circuit macro 108 (delay time 2xc3x97{tCKxe2x88x92(td1+td2)}), and the clock driver 104 (delay time=td2), so that the external clock is outputted as the internal clock 107. Therefore, the internal lock k107 has a delay time of 2tCK.
In the synchronous delay circuit, since the delay amount of tV=tCKxe2x88x92(td1+td2) is measured by knowing to which position an input signal advances in the delay circuit array 101, assuming that the delay time of the whole of the delay circuit array 101 is tDL, a maximum value of an operable period tCK becomes td1+td2+tDL.
Here, since the delay times td1 and td2 are determined by the input buffer 103 and the clock driver 104, the maximum value of the clock period tCK is determined by tDL.
On the other hand, the delay circuit arrays occupy a large area in the synchronous delay circuit. Therefore, it has been required to reduce the area of the delay circuit arrays by decreasing the number of delay circuit stages in the delay circuit array, while ensuring the maximum delay time tDL.
For example, in a prior art delay circuit disclosed by Y. OKAJIMA et al xe2x80x9cDigital Delay Locked Loop and Design Technique for High-Speed Synchronous Interfacexe2x80x9d, IEICE TRANS. ELECTRON., Vol. E79-C, No. 6, June 1996, pp798-807 (the content of which is incorporated by reference in its entirety into this application), if it is attempted to increase the delay time of each unitary delay circuit stage, it is considered to add a capacitor 1309 to the unitary delay circuit, as shown in FIG. 14. FIG. 14 illustrates one unitary delay circuit of each of the delay circuit arrays 101 and 102 shown in FIG. 1.
In brief, a unitary delay circuit of the delay circuit arrays 101 is designated with reference number 1 and is constituted of a clocked inverter including two P-channel MOS transistors 1301 and 1302 and two N-channel MOS transistors 1303 and 1304 connected in series in the named order between a high voltage power supply line VDD and ground GND. A unitary delay circuit of the delay circuit arrays 102 is designated with reference number 2 and is also constituted of a clocked inverter including two P-channel MOS transistors 1305 and 1306 and two N-channel MOS transistors 1307 and 1308 connected in series in the named order between the high voltage power supply line VDD and the ground GND. The capacitor 1309 is connected to an connection node between an output of the unitary delay circuit 1 and an input of the unitary delay circuit 2. With this addition of the capacitor, it is possible to increase the delay time of the unitary delay circuit, and therefore, it is possible to reduce the number of delay circuit stages in the delay circuit array.
However, if the delay time of the unitary delay circuit is increased by adding the capacitor to an output of each of cascade-connected unitary delay circuits, another problem is encountered in which a jitter increases as shown in FIG. 7.
The reason for this is as follows: The jitter is in proportion to a difference between a charging time through the P-channel MOS transistors included in the delay circuit and a discharging time through the N-channel MOS transistors included in the delay circuit. Therefore, if the capacitor is added between the unitary delay circuits as shown in FIG. 14, the charging time through the P-channel MOS transistor and the discharging time through the N-channel MOS transistor are respectively increased in the same way, with the result that the difference between the charging time and the discharging time is correspondingly increased, and therefore, the jitter becomes large.
Accordingly, it is an object of the present invention to provide a synchronous delay circuit which has overcome the above mentioned problem of the prior art.
Another object of the present invention is to provide a synchronous delay circuit having a reduced number of delay circuit stages in a delay circuit array by suppressing an increase of jitter.
The above and other objects of the present invention are achieved in accordance with the present invention by a synchronous delay circuit wherein a unitary delay circuit of a delay circuit array is constituted of a clocked inverter having a current limiting means inserted in series in an output node charging/discharging current path.
In one preferred embodiment of the synchronous delay circuit in accordance with the present invention, each of a plurality of unitary delay circuits included in one delay circuit array includes a CMOS inverter receiving an input signal. A P-channel MOS transistor of the CMOS inverter, a switching P-channel MOS transistor on-off controlled by a control signal, and a current limiting means are connected in series between a high voltage power supply line and an output node of the unitary delay circuit stage. An N-channel MOS transistor of the CMOS inverter, a switching N-channel MOS transistor on-off controlled by an inverted signal of the control signal, and another current limiting means are connected in series between the ground and the output node of the unitary delay circuit stage.
Specifically, the synchronous delay circuit includes a first delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages, and a second delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages arranged to have a signal propagating direction opposite to that of the first delay circuit array. Each of the delay circuit stages of the first and second delay circuit arrays is constituted of the above mentioned unitary delay circuit.
With the above mentioned arrangement, since a current drive capability of each unitary delay circuit is decreased by adding the current limiting means to each unitary delay circuit, a delay time per one unitary delay circuit can be increased, so that the number of unitary delay circuit stages in the delay circuit array required to obtain a desired delay time can be reduced, and therefore the area of the delay circuit array can also be reduced.
On the other hand, since the current drive capability of each unitary delay circuit is decreased by adding the current limiting means to each unitary delay circuit, the difference between the charging time through the P-channel MOS transistor and the discharging time through the N-channel MOS transistor does not relatively become large. Therefore, the increase of the jitter is prevented.
For example, the current limiting means can be constituted of a resistor or a CMOS transfer gate inserted in series in a charging/discharging current path of each unitary delay circuit.
In an embodiment of the synchronous delay circuit in accordance with the present invention, a delay circuit array is constituted of alternately cascade-connecting a plurality of first clocked inverters each composed of P-channel MOS transistors and a plurality of second clocked inverters each composed of N-channel MOS transistors, each of the clocked inverters having a current limiting means inserted in series in a charging/discharging current path of the clocked inverter.
In this embodiment of the synchronous delay circuit, since a current drive capability of each clocked inventor (unitary delay circuit) is decreased by adding the current limiting means to each unitary delay circuit, a similar advantage can be obtained.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.